FPR3346501R1012 ABB

FPR3346501R1012 ABB

FPR3346501R1012 main CPU scans all the inputs on the CS31 and updates the output in one cycle

FPR3346501R1012 MiU hot spare CPU monitors on the CS31 bus, which scans for all inputs but does not perform output updates

In the event of failure of the main CPU, the hot spare CPU becomes the master CPU after 3 cycles -> the output is preserved for 3 cycles, after which the hot spare CPU updates the output (if you configure the same parameters in both programs, PID loop control can be used in the program, as can timing).

In the event of a disconnection in the CS31 bus, each CPU will control a segment of the bus.

FPR3346501R1012 After the bus is reconnected, the CS31 bus is fully controlled by the hot standby CPU