DSDX451 cpus of the two hot spare systems are synchronized (the cycle period must be the same)

– %O62.08 is 1 after two cpus are synchronized

-CPU state is reflected by output bit %O62.10

– Which CPU controls the CS31 bus, its output bit %O62.10 is 1

– DSDX451 diagnostic status is given by the output bits % O62.11, %O62.12, %O62.13

– All other CS31 bus diagnostic data are accessible

– Can force either CPU to be the master station on the CS31 bus

– The words IW62.08-15 and OW62.08-15 of the two cpus are continuously advanced between them line

DSDX451

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