Before discussing Chiplet, Moore’s Law is a topic that cannot be avoided. In 1965, Gordon Moore proposed Moore’s Law: Every year the number of transistors per unit area doubles, so does the performance. This means that the number of transistors available for the same price is doubled. However, ten years later, in 1975, Mr. Moore revised the law to a period of 24 months. At this point, Moore’s Law has affected the semiconductor industry for half a century.

As integrated circuit technology continues to evolve, the semiconductor industry finds that Moore’s Law is gradually failing. The top right section of the graph shows the evolution history of Intel’s x86 cpus from 1970 to 2025, and you can see that the number of transistors per chip continues to increase (dark blue line on the top right), but the clock speed (sky blue line on the top right) and thermal design power consumption (gray line on the top right) have not changed much since 2005. At the same time, affected by the high cost of advanced processes, the decline in transistor costs has slowed down after 2012, and there is even a trend of cost increases in the future.

As can be seen from the statistics at the bottom right of the figure above, the chip process continues to shrink and evolve, and the number of transistors is also increasing correspondingly. Prior to 2019, the number of transistors per chip and the evolution of process geometry had been highly correlated with Moore’s Law. Because the number of transistors per unit area doubles each cycle, the size of the Die can ideally remain the same. However, according to the area marked green at the bottom right, it can be seen that the Die size of a single chip is increasing, which also shows from another Angle that the increase in the number of transistors on a single chip is also caused by the increase in Die. Due to the growth of Die Size, restricted by factors such as mask size and process yield, it is becoming more and more difficult to improve the computing power of a single chip by increasing Die size.

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All in all, with the development and evolution of integrated circuit technology, it has become difficult to double the number of transistors per unit area every 24 months. This means that the improvement of chip performance has now encountered a bottleneck, and performance cannot be driven solely by process technology, but also needs to be driven by architectural innovation. Therefore, the industry must find new solutions.

In the case of Moore’s Law gradually failing, Chiplet technology emerged in the semiconductor industry. Overall, Chiplet has three characteristics of high integration, high yield, and low cost, and it is regarded as a key technology to continue Moore’s Law.

Zeng Keqiang introduced that Chiplet through the integration of multiple chips, can break through the upper limit of the traditional single chip, and further improve the integration of the chip. For example, the monolithic SoC shown above is produced through a unified process, resulting in simultaneous iterations of all parts on the chip, with a development time of three to four years and hundreds of defects. The single IP integrated Chiplet in the above left image accelerates the time-to-market by cutting different functions and selectively iterating the process of some units to produce the next generation of products after iterating the chip. The integration of Chiplet chip with more widely used and mature bare chips can effectively reduce the development risk of Chiplet chip, and also reduce the number of re-flow and packaging, which can save research and development investment for chip enterprises.

Chiplet can improve the yield of complex SoC chips, which are divided into smaller chips. The larger the area of a single chip, the lower the yield, the higher the corresponding chip manufacturing cost, and the chip design cost will increase with the evolution of the process. Cutting small chips can effectively reduce the chip design cost. In addition, in SoC design, analog circuits and high-power IO are not sensitive to the process and do not need too high-end chip process. The functional modules in SoC can be divided into separate Chiplet, and the appropriate process can be selected for the function, so as to minimize the chip, improve the chip yield and reduce the chip cost.